The present invention generally relates to computer-aided circuit design systems and, more particularly, to a method and apparatus for determining which branch of a network of nodes of an integrated circuit has the largest total effective RC delay.
Integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and other components comprised on a single semiconductor xe2x80x9cchipxe2x80x9d in which the components are interconnected to perform a given function. Typical examples of integrated circuits include, for example, microprocessors, programmable logic devices (PLDs), electrically erasable programmable memory devices (EEPROMs), random access memory devices (RAMs), operational amplifiers and voltage regulators. A circuit designer typically designs the integrated circuit by using very large scale integrated (VLSI) circuit design techniques to create a circuit schematic which indicates the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and to ensure that performance goals are satisfied.
In the world of electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer aided design (E-CAD) tools. As will be appreciated by those skilled in the art, electronic devices include electrical analog, digital, mixed hardware, optical, electro-mechanical, and a variety of other electrical devices. The design and the subsequent simulation of any circuit board, VLSI chip, or other electrical device via E-CAD tools allows a product to be thoroughly tested and often eliminates the need for building a prototype. Thus, today""s sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without having to perform costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools must deal with an electronic representation of the hardware device. A xe2x80x9cnetlistxe2x80x9d is one common representation of a hardware device. As will be appreciated by those skilled in the art of hardware device design, a xe2x80x9cnetlistxe2x80x9d is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often, a netlist will contain a number of circuit xe2x80x9cmodulesxe2x80x9d which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules essentially containing no boundary differentiation between the circuit modules and other components in the device. By way of analogy, one graphical representation of a flat netlist is simply the complete schematic of the circuit device.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module which may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist would show the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules would be represented by xe2x80x9cblack boxes.xe2x80x9d As will be appreciated by those skilled in the art, a black box is a system or component whose inputs, outputs, and general function are known, but whose contents are not shown. These xe2x80x9cblack boxxe2x80x9d representations, hereinafter called xe2x80x9cmodulesxe2x80x9d, will mask the complexities therein, typically showing only input/output ports.
An integrated circuit design can be represented at different levels of abstraction, such as the Register-Transfer level (RTL) and the logic level, using a hardware description language (HDL). VHDL and Verilog are examples of HDL languages. At any abstraction level, an integrated circuit design is specified using behavioral or structural descriptions, or a mix of both. At the logical level, the behavioral description is specified using boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are full-adders, NAND gates, latches, and D-Flip Flops.
Having set forth some very basic information regarding the representation of integrated circuits and other circuit schematics through netlists, systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally such systems identify certain critical timing paths, and then evaluate the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
One such system known in the prior art is marketed under the name PathMill, by EPIC Design Technology, Inc., subsequently purchased by Synopsis, Inc. PathMill is a transistor-based analysis tool used to find critical paths and to verify timing in semiconductor designs. Using static and mixed-level timing analysis, PathMill processes transistors, gates, and timing models. It also calculates timing delays, performs path searches, and checks timing requirements. As is known, PathMill can analyze combinational designs containing gates, and sequential designs containing gates, latches, flip-flops, and clocks. Combinational designs are generally measured through the longest and shortest paths.
While tools such as these are useful for the design verification process after layout, there are various shortcomings in the PathMill product and other similar products. One primary shortcoming of the PathMill program is that it does not analyze the circuits to determine the design quality of the circuits. Rather, the PathMill program performs a static timing analysis of a circuit using the netlist provided to the PathMill program. Furthermore, configuring the PathMill program to recognize various circuit characteristics is typically a very difficult task.
Accordingly, a need exists for a rules checking system that will allow circuits to be evaluated for design quality. The present invention works in conjunction with a tool, such as, for example, the PathMill program, to evaluate the design quality of network nodes of an integrated circuit. Typically, such tools, including the PathMill program, receive a netlist and use the netlist to determine FET (field effect transistor) direction, node types, latches, dynamic gates, rise and fall times, etc. This information is utilized by the rules checking system of the present invention to evaluate the design quality of networks of an integrated circuit.
In accordance with the present invention, the rules checking system evaluates the design quality of networks of an integrated circuit to determine which branch of a network corresponds to the largest total effective RC delay. This total effective RC delay may then be used to make other determinations, such as, for example, to determine the skew of the processor clock that controls the timing of the integrated circuit.
The present invention provides a method and apparatus for determining the RC delays associated with branches of a network comprised in an integrated circuit. The apparatus comprises logic configured to execute a rules checker algorithm. When the rules checker algorithm is executed, the algorithm analyzes information relating to the network and determines the RC delays between the output of a driver gate of the network and the inputs of one or more receiver gates of the network.
In accordance with the preferred embodiment of the present invention, the rules checker algorithm performs these tasks by: (1) analyzing each branch of the network to determine the primary RC delay of each branch assuming the branch being analyzed corresponds to the worst case RC delay of the network; (2) analyzing each branch of the network assuming one of the other branches of the network corresponds to the worst case RC delay of the network and determining the effect that the resistors and capacitors of the branch being analyzed would have on other branches; (3) determining the total effective RC delay of each branch by combining the effect that the other branches have on the branch being analyzed with the primary RC delay of the branch being analyzed; and (4) determining which branch of the network has the largest total effective RC delay.
These and other features and advantages of the present invention will become apparent from the following description, drawings and claims.